#How to make makefile for c program how to#
#How to make makefile for c program series#

The beauty of this command is that it knows which files have changed since the last time it was executed, and builds only those dependencies that are required. To clean all the extra object files and the test executable file, before you start a compilation cycle. So you can just issue the following command : make clean Similarly, If you want to remove all the non-required object or executable files before every cycle of compilation, you can add a target clean to your Makefile. Then this command would scan the Makefile, build (if required) the dependencies of test and then execute the command to build test itself. For example, if you specify the following command : make test

#How to make makefile for c program how to#

This command accepts a target as an argument and looks for a file named 'Makefile' to understand how to build that target. Now, one would ask, how to use these targets? Well, these are used through the 'make' command. c files, and can be produced through the respective commands mentioned below them.

Similarly, the targets 'test.o' and 'anotherTest.o' both depend on their corresponding.

The target 'test' depends on test.o and anotherTest.o, and can be produced through the command mentioned below it.The target 'all' is nothing but a default makefile target.This may look a bit complicated to a beginner but if you observe closely, it contains nothing but groups of targets, dependencies and commands. Gcc -Wall test.c anotherTest.c -o test -I.

So, if we want to create a very basic makefile for our example project (listed in last section), it would be something like : all: test In a layman's terms, here is a very basic syntax of a makefile : target: dependencies MakefilesĪ makefile is a special file (named as 'Makefile' only) that consists of targets, dependencies and commands, structured in a way that makes it easy for a programmer to compile the program. Wouldn't it be inefficient for a program to take 10 minutes to compile, even if a single line is changed/added in one of the source files? c files but use a single command to recompile. Now, suppose you add a simple printf debug line in one of the. But, what if you somehow loose this command or switch to another system? Will you again type the long command?Īlso, suppose your project grows into a big project that contains hundreds of files, and takes 5-10 minutes to compile. Many would argue that they will extend the existing command by adding the names of those new files. Now suppose, your project grows and now contains 10 more source and header files. This is fine as long as your project contains just a few files.

Suppose your project consists of the following three files kept in a directory: test.cĪs a beginner, you'll run the following command again and again to compile your project : gcc -Wall test.c anotherTest.c -o test -I.

#How to make makefile for c program series#

This topic would be covered in a series of articles and in this first part, we will discuss the very basics of makefiles in Linux. But, as their projects start to grow, compilation through a single command does not remain easy and effective.Īs a solution to all the compilation related problems, you need to understand the concept of makefiles.

As beginners, most of the C/C++ programmers compile their programs on Linux command line by running the gcc or g++ compiler commands.